MB15F78SP 查看數據表（PDF） - Fujitsu

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MB15F78SP

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F78SP

3. Power Saving Mode (Intermittent Mode Control Circut)

Status

PSTX/PSRX pins

Normal mode

H

Power saving mode

L

The intermittent mode control circuit reduces the PLL power consumption.

By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption.

See the Electrical Characteristics chart for the specific value.

The phase detector output, Do, becomes high impedance.

For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.

Setting the PS pins high, releases the power saving mode, and the device works normally.

The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.

When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is

because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)

which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase

in lockup time.

To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error

signal from the phase detector when it returns to normal operation.

Notes: •When power (VCC) is first applied, the device must be in standby mode, PSTX = PSRX = Low, for at least 1 µs.

•PS pins must be set at “L” for Power-ON

VCC

Clock

Data

LE

PSTX

PSRX

OFF

ON

tV ≥ 1 µs

(1)

(2)

tPS ≥ 100 ns

(3)

(1) PSTX = PSRX = “L” (power saving mode) at Power-ON

(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).

(3) Release power saving mode (PSTX, PSRX : “L” → “H”) 100 ns later after setting serial data.

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