AC OPERATING CONDITIONS AND CHARACTERISTICS
(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Clock Input Timing Reference Level . . . . . . Differential Cross–Point
Clock Input Pulse Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 V to 2.1 V
READ/WRITE CYCLE TIMING (See Note 1)
MCM69L737A–8.5 MCM69L737A–9 MCM69L737A–9.5
MCM69L819A–8.5 MCM69L819A–9 MCM69L819A–9.5
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit Notes
Cycle Time
tKHKH
8
—
8
—
9
—
ns
Clock High Pulse Width
tKHKL
3.2
—
3.2
—
3.6
—
ns
Clock Low Pulse Width
tKLKH
3.2
—
3.2
—
3.6
—
ns
Clock High to Output Valid
tKHQV
—
8.5
—
9
—
9.5
ns
Clock Low to Output Valid
tKLQV
—
3.5
—
3.5
—
4
ns
Clock Low to Output Hold
tKLQX
0.5
—
0.5
—
0.5
—
ns
2
Clock Low to Output Low–Z
tKLQX1
1
—
1
—
1
—
ns
2, 3
Clock High to Output High–Z
tKHQZ
1
3.5
1
3.5
1
4
ns
2, 3
Output Enable Low to Output Low–Z
tGLQX
0.5
—
0.5
—
0.5
—
ns
Output Enable Low to Output Valid
tGLQV
—
3.5
—
3.5
—
4
ns
Output Enable to Output Hold
tGHQX
0.5
—
0.5
—
0.5
—
ns
Output Enable High to Output High–Z
tGHQZ
—
3.5
—
3.5
—
4
ns
2, 3
Setup Times:
Address tAVKH
0.5
—
0.5
—
0.5
—
ns
Data In tDVKH
Chip Select tSVKH
Write Enable tWVKH
Hold Times:
Address tKHAX
1
—
1
—
1
—
ns
Data In tKHDX
Chip Select tKHSX
Write Enable tKHWX
NOTES:
1. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g., tKHKL) or at frequencies that exceed the applied K clock frequency.
2. This parameter is sampled, and not 100% tested.
3. Measured at ± 200 mV from steady state.
MOTOROLA FAST SRAM
MCM69L737A•MCM69L819A
7