MCM69R736A 查看數據表（PDF） - Motorola => Freescale

零件编号

产品描述 (功能)

生产厂家

MCM69R736A

4M Late Write HSTL

Motorola => Freescale 

MCM69R818A PIN DESCRIPTIONS

PBGA Pin Locations

4K

4L

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P

(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P

4F

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,

6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T

5L, 3G

(a), (b)

4E

4M

4U

3U

5U

2U

4D

7T

4C, 2J, 4J, 6J, 4R, 5R

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U

3J, 5J

3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,

3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R

4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,

2D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,

2H, 4H, 7H, 1K, 6K, 2L, 7L, 6M, 2N,

7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U

Symbol

CK

CK

DQx

Type

Input

Input

I/O

Description

Address, data in and control input register clock. Active high.

Address, data in and control input register clock. Active low.

Synchronous Data I/O.

G

Input Output Enable: Asynchronous pin, active low.

SA

Input Synchronous Address Inputs: Registered on the rising clock edge.

SBx

SS

SW

TCK

TDI

TDO

TMS

ZQ

ZZ

VDD

VDDQ

Vref

VSS

Input

Synchronous Byte Write Enable: Enables writes to byte x in

conjunction with the SW input. Has no effect on read cycles, active

low.

Input Synchronous Chip Enable: Registered on the rising clock edge, active

low.

Input Synchronous Write: Registered on the rising clock edge, active low.

Writes all enabled bytes.

Input Test Clock (JTAG).

Input Test Data In (JTAG).

Output Test Data Out (JTAG).

Input Test Mode Select (JTAG).

Input Programmable Output Impedance: Programming pin.

Input Enables sleep mode, active high.

Supply Core Power Supply.

Supply Output Power Supply: provides operating power for output buffers.

Supply Input Reference: provides reference voltage for input buffers.

Supply Ground.

NC

— No Connection: There is no connection to the chip.

MCM69R736A•MCM69R818A

4

MOTOROLA FAST SRAM

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