ISL6112EVAL1Z 查看數據表（PDF） - Renesas Electronics
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ISL6112EVAL1Z Datasheet PDF : 30 Pages
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ISL6112
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
PIN FUNCTION
14, 23
3VGATEA 3VGATEB
3V gate drive outputs. Each pin connects to the gate of an external N-Channel MOSFET. During power-up, the
CGATE and the CGS of the MOSFETs are connected to a 25µA current source. This controls the value of dv/dt
seen at the source of the MOSFETs, and hence the current flowing into the load capacitance. During current
limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of
tFLT. Whenever an overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the GATE pin
for the affected slot is immediately brought low. During power-down, these pins are discharged by an internal
current source.
11, 26
VSTBYA, VSTBYB
3.3V standby input voltage. Required to support PCI-Express VAUX output. Additionally, the SMBus logic and
internal registers run off of VSTBY to ensure that the chip is accessible during standby modes. A UVLO circuit
prevents turn-on of this supply until VSTBY rises above its UVLO threshold. Both pins must be externally
connected together at the ISL6112 controller.
15, 22
VAUXA, VAUXB
3.3VAUX outputs to PCI-Express card slots. These outputs connect the 3.3AUX pin of the PCI-Express
connectors to VSTBY via internal 400m MOSFETs. These outputs are 1A current limited and protected
against short-circuit faults.
44, 43
ONA, ONB
Enable inputs. Rising-edge triggered. Used to enable or disable the MAINA and MAINB (+3.3V and +12V)
outputs. Taking ON low after a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie these
pins to GND if using SMI power control. Also see pin descriptions for FAULTA and FAULTB.
45, 42
AUXENA, AUXENB Level sensitive auxiliary enable inputs. Used to enable or disable the VAUX outputs. Taking AUXEN low after a
fault resets the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power control. Also
see pin descriptions for FAULTA and FAULTB.
2, 35
CFILTERA, CFILTERB Overcurrent timers. Capacitors connected between these pins and GND set the duration of CRTIM. CRTIM is
the amount of time for which a slot remains in current limit before its isolation protection is invoked.
6, 31
1, 36
PWRGDA PWRGDB Power-is-Good outputs. Open-drain, active-low. Asserted when a slot has been commanded to turn on and has
successfully begun delivering power to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an
external pull-up resistor to VSTBY.
FAULTA, FAULTB
Fault outputs. Open-drain, active-low. Asserted whenever the isolation protection trips due to a fault condition
(overcurrent, input undervoltage, over-temperature). Each pin requires an external pull-up resistor to VSTBY.
Bringing the slot’s ON pin low resets FAULT, if FAULT was asserted in response to a fault condition on one of
the slot’s MAIN outputs (+12V or +3.3V). FAULT is reset by bringing the slot’s AUXEN pin low if FAULT was
asserted in response to a fault condition on the slot’s VAUX output. If a fault condition occurred on both the
MAIN and VAUX outputs of the same slot, then both ON and AUXEN must be brought low to de-assert the FAULT
output.
9, 28
FORCE_ONA
FORCE_ONB
Enable inputs. Active-low, level-sensitive. Asserting a FORCE_ON input turns on all three of the respective
slot’s outputs (+12V, +3.3V, and VAUX) while specifically defeating all protections on those supplies. This
explicitly includes all overcurrent and short-circuit protections, and on-chip thermal protection for the VAUX
supplies. Additionally included are the UVLO protections for the +3.3V and +12VMAIN supplies. The
FORCE_ON pins do not disable UVLO protection for the VAUX supplies. These input pins are intended for
diagnostic purposes only. Asserting FORCE_ON causes the respective slot’s PWRGD and FAULT pins to enter
their open-drain state. Note that the SMBus register set continues to reflect the actual state of each slot’s
supplies. There is a pair of register bits, accessible via the SMBus, which can be set to disable (unconditionally
de-assert) either or both of the FORCE_ON pins; see CNTRL Register Bit D[2].
4, 38
GPI_A0, GPI_B0 General purpose inputs. The states of these two inputs are available by reading the Common Status Register,
Bits [4:5]. If not used, connect each pin to GND.
39, 40, 41
48
A2, A1, A0
SDA
SMBus address select pins. Connect to ground or leave open in order to program device SMBus base address.
These inputs have internal pull-up resistors to VSTBY. Address programmed on rising VSTBY.
Bidirectional SMBus data line.
47
SCL
SMBus clock input.
37
17, 33, 46
INT
Interrupt output. Open-drain, active-low output. Asserted whenever a power fault is detected if the INTMSK bit
(CS Register Bit D[3]) is a logical “0”. This output is cleared by performing an “echo reset” to the appropriate
fault bits in the STAT or CS registers. This pin requires an external pull-up resistor to VSTBY.
GND
IC reference pins. Connect together and tie directly to the system’s analog GND plane directly at the device.
7, 18, 19, 20, 30
NC
Reserved. Make no external connections to these pins.
FN6456 Rev 1.00
August 25, 2011
Page 5 of 30
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