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ISL59452IRZ 查看數據表(PDF) - Renesas Electronics

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ISL59452IRZ Datasheet PDF : 15 Pages
First Prev 11 12 13 14 15
ISL59452
Typical Performance Curves V+ = +5V, RL = 150to GND, CL = 0.6pF, TA = +25°C, unless otherwise specified. (Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1.0
0.8
758mW
0.6
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3.0
2.857W
2.5
QFN32
2.0
JA = 35°C/W
1.5
0.4
QFN32
1.0
JA = 125°C/W
0.2
0.5
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Functional Block Diagram (Each Output
Channel)
AV2
S0
S1
R0/G0/B0
V+
R1/G1B/1
R2/G2/B2
R3/G3/B3
ROUT
x2/1
GOUT
BOUT
GND
TABLE 1. CHANNEL SELECT LOGIC TABLE
S1
S0
HIZ
OUTPUT
0
0
0
R0, G0, B0
0
1
0
R1, G1, B1
1
0
0
R2, G2, B2
1
1
0
R3, G3, B3
X
X
1
High Impedance,
Inputs Disconnected
© Copyright Intersil Americas LLC 2007. All Rights Reserved.
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For additional products, see www.intersil.com/en/products.html
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6254 Rev 0.00
September 24, 2007
Page 11 of 15

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