HI5662 查看數據表（PDF） - Renesas Electronics

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HI5662

Dual 8-Bit, 60MSPS A/D Converter with Internal Voltage Reference

Renesas Electronics 

HI5662

TABLE 1. A/D CODE TABLE

OFFSET BINARY OUTPUT CODE

CODE CENTER

DESCRIPTION

+Full Scale (+FS) -7/16LSB

+FS - 17/16LSB

+9/16LSB

-7/16LSB

-FS + 19/16LSB

-Full Scale (-FS) + 9/16LSB

DIFFERENTIAL INPUT

VOLTAGE

(I/QIN+ - I/QIN-)

0.498291V

0.494385V

2.19727mV

-1.70898mV

-0.493896V

-0.497803V

MSB

I/QD7

1

1

1

0

0

0

I/QD6

1

1

0

1

0

0

I/QD5

1

1

0

1

0

0

I/QD4

1

1

0

1

0

0

I/QD3

1

1

0

1

0

0

I/QD2

1

1

0

1

0

0

I/QD1

1

1

0

1

0

0

NOTE:

8. The voltages listed above represent the ideal center of each output code shown with VREFIN = +2.5V.

LSB

I/QD0

1

0

0

1

1

0

Detailed Description

Theory of Operation

The HI5662 is a dual 8-bit fully differential sampling pipeline

A/D converter with digital error correction logic. Figure 14

depicts the circuit for the front end differential-in-differential-out

sample-and-hold (S/H) amplifiers. The switches are controlled

by an internal sampling clock which is a non-overlapping two

phase signal, 1 and 2, derived from the master sampling

clock. During the sampling phase, 1, the input signal is

applied to the sampling capacitors, CS. At the same time the

holding capacitors, CH, are discharged to analog ground. At

the falling edge of 1 the input signal is sampled on the bottom

plates of the sampling capacitors. In the next clock phase, 2,

the two bottom plates of the sampling capacitors are

connected together and the holding capacitors are switched to

the op-amp output nodes. The charge then redistributes

between CS and CH completing one sample-and-hold cycle.

The front end sample-and-hold output is a fully-differential,

sampled-data representation of the analog input. The circuit

not only performs the sample-and-hold function but will also

convert a single-ended input to a fully-differential output for the

converter core. During the sampling phase, the I/QIN pins see

only the on-resistance of a switch and CS. The relatively small

values of these components result in a typical full power input

bandwidth of 250MHz for the converter.

I/QIN+

I/QIN-

1

2

1

1

CS

CS

1

CH

-+

+-

CH

1

VOUT+

VOUT-

1

FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD

As illustrated in the functional block diagram and the timing

diagram in Figure 1, identical pipeline subconverter stages,

each containing a two-bit flash converter and a two-bit

multiplying digital-to-analog converter, follow the S/H circuit

with the last stage being a two bit flash converter. Each

converter stage in the pipeline will be sampling in one phase

and amplifying in the other clock phase. Each individual

subconverter clock signal is offset by 180 degrees from the

previous stage clock signal resulting in alternate stages in the

pipeline performing the same operation.

The output of each of the identical two-bit subconverter stages

is a two-bit digital word containing a supplementary bit to be

used by the digital error correction logic. The output of each

subconverter stage is input to a digital delay line which is

controlled by the internal sampling clock. The function of the

digital delay line is to time align the digital outputs of the

identical two-bit subconverter stages with the corresponding

output of the last stage flash converter before applying the

results to the digital error correction logic. The digital error

correction logic uses the supplementary bits to correct any

error that may exist before generating the final eight bit digital

data output of the converter.

Because of the pipeline nature of this converter, the digital data

representing an analog input sample is output to the digital

data bus following the 6th cycle of the clock after the analog

sample is taken (see the timing diagram in Figure 1). This time

delay is specified as the data latency. After the data latency

time, the digital data representing each succeeding analog

sample is output during the following clock cycle. The digital

output data is provided in offset binary format (see Table 1, A/D

Code Table).

Internal Reference Voltage Output, VREFOUT

The HI5662 is equipped with an internal reference voltage

generator, therefore, no external reference voltage is required.

VROUT must be connected to VRIN when using the internal

reference voltage.

FN4317 Rev 2.00

February 1999

Page 11 of 15

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