MC10111 查看數據表（PDF） - ON Semiconductor
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MC10111 Datasheet PDF : 5 Pages
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MC10111
Dual 3−Input/3−Ouput NOR
Gate
The MC10111 is designed to drive up to three transmission lines
simul− taneously. The multiple outputs of this device also allow the
wire “OR”−ing of several levels of gating for minimization of gate and
package count.
The ability to control three parallel lines from a single point makes
the MC10111 particularly useful in clock distribution applications
where minimum clock skew is desired. Three VCC pins are provided
and each one should be used.
• PD = 80 mW typ/gate (No Load)
• tpd = 2.4 ns typ (All Outputs Loaded)
• tr, tf = 2.2 ns typ (20%−80%)
LOGIC DIAGRAM
2
5
3
6
4
7
12
9
13
10
14
11
VCC1 = PIN 1,15
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
AOUT
3
AOUT
4
AIN
5
AIN
6
AIN
7
VEE
8
16
VCC2
15
VCC1
14
BOUT
13
BOUT
12
BOUT
11
BIN
10
BIN
9
BIN
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP−16
L SUFFIX
CASE 620
PDIP−16
P SUFFIX
CASE 648
PLCC−20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10111L
AWLYYWW
1
16
MC10111P
AWLYYWW
1
1
10111
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10111L
CDIP−16
25 Units / Rail
MC10111P
PDIP−16
25 Units / Rail
MC10111FN
PLCC−20 46 Units / Rail
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 8
Publication Order Number:
MC10111/D
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