DM74ALS652NT 查看數據表（PDF） - Fairchild Semiconductor

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DM74ALS652NT

Octal 3-STATE Bus Transceiver and Register

Fairchild Semiconductor 

Function Table

GAB

GBA

Inputs

CAB CBA

SAB

SBA

Data I/O (Note 1)

A1 thru A8 B1 thru B8

Operation or Function

X

H

↑

H/L

X

X

Input

Not Specified Store A, Hold B

L

X

H/L

↑

X

X Not Specified

Input

Store B, Hold A

L

H

↑

↑

X

X

Input

Input

Store A and B Data

L

H

H/L

H/L

X

X

Input

Input

Isolation, Hold Storage

L

L

X

X

X

L

Output

Input

Real-Time B Data to A Bus

L

L

X

H/L

X

H

Output

Input

Stored B Data to A Bus

H

H

X

X

L

X

Input

Output Real-Time A Data to B Bus

H

H

↑

↑

X

X

Input

Output Stored A Data to B Bus

H

H

↑

↑

X

X

(Note 2)

Input

Output Store A in both Registers

L

L

↑

↑

X

X

Output

(Note 2)

Input

Store B in both Registers

H

L

H or L H or L

H

H

Output

Output

Stored A Data to B Bus and

Stored B Data to A Bus

H = HIGH Logic Level

L = LOW Logic Level

X = Don’t Care (Either LOW or HIGH Logic Levels, including transitions)

H/L = Either LOW or HIGH Logic Level excluding transitions

↑ = Positive-going edge of pulse

Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled,

i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

Note 2: Select control = L; clocks can occur simultaneously

Select control = H; clocks must be staggered in order to load both registers.

Logic Diagram

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