TDA8034AT 查看數據表（PDF） - NXP Semiconductors.

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TDA8034AT

Smart card interface

NXP Semiconductors. 

NXP Semiconductors

TDA8034T; TDA8034AT

Smart card interface

8.4 Input and output circuits

When pins I/O and I/OUC are pulled HIGH using an 11 k resistor between pins I/O and

VCC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is

referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC  VDD(INTF).

The first side on which a falling edge occurs becomes the master. An anti-latch circuit

disables falling edge detection on the other line, making it the slave. After a time delay td,

the logic 0 present on the master-side is sent to the slave-side. When the master-side

returns logic 1, the slave-side sends logic 1 during time delay (tw(pu)). After this sequence,

both master and slave sides return to their idle states.

The active pull-up feature ensures fast LOW-to-HIGH transitions making the

TDA8034T/TDA8034AT capable of delivering more than 1 mA, up to an output voltage of

0.9VCC, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is

dependent on the internal pull-up resistor value and load current. The current sent to and

received from the card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.

TDA8034T_TDA8034AT

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3.1 — 13 December 2012

© NXP B.V. 2012. All rights reserved.

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