AD5247 查看數據表（PDF） - Analog Devices
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AD5247 Datasheet PDF : 20 Pages
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AD5247
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
Table 1. VDD = 5 V ±10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C; unless otherwise noted
Parameter
Symbol Conditions
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
Capacitance6 A
Capacitance6 W
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
POWER SUPPLIES
R-DNL
R-INL
∆RAB
∆RAB/∆T
RWB
DNL
INL
∆VW/∆T
VWFSE
VWZSE
VB, W
CA
CW
ICM
VIH
VIL
VIH
VIL
IIL
CIL
RWB, VA = No Connect
RWB, VA = No Connect
VA = VDD, Wiper = No Connect
Code = 0x00
Code = 0x40
Code = 0x7F
Code = 0x00
f = 1 MHz, Measured to GND,
Code = 0x40
f = 1 MHz, Measured to GND,
Code = 0x40
VA = VDD/2
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
Power Supply Range
Supply Current
Power Dissipation7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
VDD RANGE
IDD
PDISS
PSSR
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = +5 V ± 10%,
Code = Midscale
BW_5K
THDW
tS
eN_WB
RAB = 5 kΩ, Code = 0x40
VA = 1 V rms, VB = 0 V,
f = 1 kHz
VA = 5 V, ±1 LSB Error Band
RWB = 2.5 kΩ, RS = 0 Ω
Min Typ1 Max Unit
–1.5 ±0.1 +1.5 LSB
–4 ±0.75 +4 LSB
–30
+30 %
45
ppm/°C
75
300 Ω
–1 ±0.1 +1
–1 ±0.2 +1
15
–3 –2
0
0
+1
+2
LSB
LSB
ppm/°C
LSB
LSB
GND
45
60
1
VDD
V
pF
pF
nA
2.4
2.1
5
V
0.8 V
V
0.6 V
±1 µA
pF
2.7
3
5.5 V
8
µA
40 µW
±0.003 ±0.05 %/%
1.2
MHz
0.05
%
1
µs
6
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
Rev. 0 | Page 3 of 20
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