AD5247 查看數據表（PDF） - Analog Devices

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AD5247

128-Position I2C Compatible Digital Potentiometer

Analog Devices 

AD5247

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 3. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted

Parameter

Symbol Conditions

I2C INTERFACE TIMING CHARACTERISTICS2, 3

(Specifications Apply to All Parts)

SCL Clock Frequency

fSCL

tBUF Bus Free Time between STOP and START

t1

tHD;STA Hold Time (Repeated START)

t2

tLOW Low Period of SCL Clock

t3

tHIGH High Period of SCL Clock

t4

tSU;STA Setup Time for Repeated START Condition

t5

tHD;DAT Data Hold Time

t6

tSU;DAT Data Setup Time

t7

tF Fall Time of Both SDA and SCL Signals

t8

tR Rise Time of Both SDA and SCL Signals

t9

tSU;STO Setup Time for STOP Condition

t10

After this period, the first clock pulse is

generated.

Min Typ1 Max Unit

400 kHz

1.3

µs

0.6

µs

1.3

µs

0.6

50 µs

0.6

µs

0.9 µs

100

ns

300 ns

300 ns

0.6

µs

1 Typical specifications represent average readings at 25°C and VDD = 5 V.

2 Guaranteed by design and not subject to production test.

3 See timing diagrams (Figure 31, Figure 32, Figure 33) for locations of measured values.

Rev. 0 | Page 5 of 20

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