GA1088MC700 查看數據表（PDF） - TriQuint Semiconductor
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GA1088MC700 Datasheet PDF : 10 Pages
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GA1088
AC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C)
Symbol
Input Clock (REFCLK)
Test Conditions (Figure 3) 1
Min
t CPWH
CLK pulse width HIGH
Figure 4
3
t CPWL
CLK pulse width LOW
Figure 4
3
t IR
Input rise time (0.8 V - 2.0 V)
—
Typ
Max
Unit
---
—
ns
---
—
ns
—
2.0
ns
Symbol
Input Clock (Q0–Q10)
Test Conditions (Figure 3) 1
Min
Typ
Max
Unit
t OR,t OF
t PD1 2
t PD2 2
t SKEW1 3
t SKEW2 3
t SKEW3 3
t SKEW4 3
t CYC 4
t JP 5
t JR 5
t SYNC 6
Rise/fall time (0.8 V – 2.0 V)
Figure 4
CLK Î to FBIN Î (GA1088-MC500)
Figure 4
CLK Î to FBIN Î (GA1088-MC700)
Figure 4
Rise–rise, fall–fall (within group)
Figure 5
Rise–rise, fall–fall (group-to-group, aligned) Figure 6 (skew2 takes into account skew1)
Rise–rise, fall–fall (group-to-group, non-aligned)Figure 7 (skew3 takes into account skews1, 2)
Rise-fall, fall-rise
Figure 8 (skew4 takes into account skew3)
Duty-cycle Variation
Figure 4
Period-to-Period Jitter
Figure 4
Random Jitter
Figure 4
Synchronization Time
350
–850
–1050
—
—
—
—
–1000
—
—
—
—
1400
ps
–350
+150
ps
–350
+350
ps
60
150
ps
75
350
ps
—
650
ps
—
1200
ps
0
+1000
ps
80
200
ps
190
400
ps
10
500
µs
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock. tJP is the jitter on the
output with respect to the output’s previous rising edge.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the
outputs to FBIN.
Figure 3. AC Test Circuit
+5 V
R1
Z
R2
+5 V
R1
Z
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y+Z=X
Y
FBIN Q0
Q1
Q2
•
•
•
•
CLK Q10
50 Ω
X
•
•
•
•
+5 V
R1 +5 V
R2 R1
R2
+5 V
R1
R2
For additional information and latest specifications, see our website: www.triquint.com
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