VG26S17405J-6 查看數據表（PDF） - Vanguard International Semiconductor
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VG26S17405J-6 Datasheet PDF : 27 Pages
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VIS
VG26(V)(S)17405FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
AC Characteristics
(Ta = 0 to + 70°C, Vcc = 5V ±10 % or 3.3V (+10%,-5%), Vss = 0V) *1, *2, *3, *4
Test conditions
• Output load: two TTL Loads and 50pF (V CC = 5.0V ±10 %)
one TTL Load and 30pF (VCC = 3.3V (+10%,-5%))
• Input timing reference levels:
VIH = 2.4V, VIL = 0.8V (VCC = 5.0V ±10 %); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V(+10%,-5%) )
• Output timing reference levels:
VOH = 2.0V, VOL = 0.8V (VCC = 5V ±10 %, 3.3V (+10%,-5%))
Read, Write, Read- Modify- Write and Refresh Cycles
(Common Parameters)
Parameter
Random read or write cycle time
RAS precharge time
CAS precharge time in normal mode
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
Column address to RAS lead time
RAS hold time
CAS hold time
CAS to RAS precharge time
OE to Din delay time
Transition time (rise and fall)
Refresh period
Refresh period (S- Version)
CAS to output in Low- Z
CAS delay time from Din
OE delay time from Din
Symbol
tRC
tRP
tCPN
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRAL
tRSH
tCSH
tCRP
tOED
tT
tREF
tREF
tCLZ
tDZC
tDZO
VG26(V)(S) 17405
Unit
-5
-6
Min Max Min Max
84
- 104
- ns
30
-
40
- ns
10
-
10
- ns
50 10000
60 10000 ns
8 10000
10 10000 ns
0
-
0
- ns
8
-
10
- ns
0
-
0
- ns
8
-
10
- ns
12
37
14
45 ns
10
25
12
30 ns
25
-
30
- ns
8
-
10
- ns
38
-
40
- ns
5
-
5
- ns
12
-
15
- ns
1
50
1
50 ns
-
32
-
32 ms
- 128
- 128 ms
0
-
0
- ns
0
-
0
- ns
0
-
0
- ns
Notes
5
6
7
8
9
10
11
Document:1G5-0162
Rev.1
Page 10
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