LP62S4096E-T 查看數據表（PDF） - AMIC Technology

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LP62S4096E-T

512K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

Timing Waveforms

Read Cycle 1(1)

Address

OE

CE1

tRC

tAA

tOE

tOLZ5

LP62S4096E-T Series

tOH

CE2

DOUT

Read Cycle 2 (1, 2, 4)

Address

DOUT

Read Cycle 3 (1, 3, 4)

CS1

tACE1 , tACE2

tCLZ1 , tCLZ2

tRC

tAA

tOH

tOHZ5

tCHZ1 , tCHZ2

tOH

CS2

DOUT

tACS1 , tACS2

tCLZ1 , tCLZ2

tCHZ1 , tCHZ2

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled, CE1 = VIL or CE2= VIH.

3. Address valid prior to or coincident with CE1 transition low or CE2 transition high.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

(May, 2010, Version 3.3)

5

AMIC Technology, Corp.

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