ISL12008IB8Z 查看數據表（PDF） - Renesas Electronics
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ISL12008IB8Z Datasheet PDF : 19 Pages
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ISL12008 I2C Real Time Clock with Battery Backup
Serial Interface Specifications Recommended Operating Conditions. Unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 8) (Note 5) (Note 8) UNITS NOTES
fSCL
tIN
SCL Frequency
Pulse width Suppression Time at SDA and
SCL Inputs
Any pulse narrower than the max
spec is suppressed.
400
kHz
50
ns
tAA
tBUF
SCL Falling Edge to SDA Output Data Valid
Time the Bus Must be Free Before the Start
of a New Transmission
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window.
SDA crossing 70% of VDD during
a STOP condition, to SDA
crossing 70% of VDD during the
following START condition.
1300
900
ns
ns
tLOW Clock LOW Time
Measured at the 30% of VDD
1300
ns
crossing.
tHIGH Clock HIGH Time
Measured at the 70% of VDD
600
ns
crossing.
tSU:STA START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
tSU:STO STOP Condition Setup Time
tHD:STO STOP Condition Hold Time
tDH
Output Data Hold Time
tR
SDA and SCL Rise Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
From SDA exiting the 30% to 70%
of VDD window, to SCL rising edge
crossing 30% of VDD.
From SCL falling edge crossing
30% of VDD to SDA entering the
30% to 70% of VDD window.
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
From SDA rising edge to SCL
falling edge. Both crossing 70% of
VDD.
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
From 30% to 70% of VDD
600
600
100
20
600
600
0
20 +
0.1 x Cb
ns
ns
ns
900
ns
ns
ns
ns
300
ns
6, 7
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1 x Cb
300
ns
6, 7
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
6, 7
Rpu SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by tR
1
and tF.
For Cb = 400pF, max is about
2k to~2.5k.
For Cb = 40pF, max is about 15k
to ~20k
k
6, 7
NOTES:
2. FT/OUT inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
5. Typical values are for T = +25°C and 3.3V supply voltage.
6. Limits should be considered typical and are not production tested.
7. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
FN6690 Rev 1.00
Sep 26, 2008
Page 4 of 19
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