XWM2152CDT/V 查看數據表（PDF） - Wolfson Microelectronics plc

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XWM2152CDT/V

12-bit, 30MSPS ADC

Wolfson Microelectronics plc 

WM2152

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Analogue Input

at VINP, VINM

Sample 1

tAD

Sample 2

Sample 3

tCLK

tCH

tCL

CLK

Sample 4

Digital Output D[[11:0]

5 x tCLK

Sample 5

Sample 6

Sample 7

tPD

Sample 1

Sample 2

Sample 3

Figure 1. Input and output timing

OEB

Digital Output D[[11:0]

tDEN

tDZ

Data

Data

Data

Data

Hi-Z

Hi-Z

Figure 2. Output enable timing

Test Conditions:

AVDD1 = AVDD2 = DVDD = 3.3V, fCLK = 30MHz, EXTREF = AGND, Mode=1, TA = TMIN to TMAX, unless otherwise stated.

PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

MAX

UNIT

Timing

Clock period

tCLK

33.3

ns

Clock low or high

tCH, tCL

15

16.6

ns

Pipeline delay

5

CLK cycles

Clock to data valid

tPD

19

ns

Output disable to hi-Z output

tDZ

3.2

ns

Output enable to data valid

tDEN

16

19

ns

PP Rev 1.2 August 2001

6

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