HD-6408 查看數據表（PDF） - Renesas Electronics
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HD-6408 Datasheet PDF : 12 Pages
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HD-6408
Encoder Operation
The Encoder requires a single clock with a frequency of twice
the desired data rate applied at the SClock input. An auxiliary
divide by six counter is provided on chip which can be utilized
to produce the SClock by dividing the DClock.
The Encoder’s cycle begins when EE is high during a falling
edge of ESC (1). This cycle lasts for one word length or twenty
ESC periods. At the next low-to-high transition of the ESC, a
high at SS input actuates a Command sync or a low will
produce a Data sync for that word (2). When the Encoder is
ready to accept data, the SD output will go high and remain
high for sixteen ESC periods (3) - (4).
During these sixteen periods the data should be clocked into
the SD Input with every high-to-low transition of the ESC (3) -
(4). After the sync and Manchester II encoded data are
transmitted through the BOO and BZO outputs, the Encoder
adds on an additional bit which is the (odd) parity for that word
(5). If ENCODER ENABLE is held high continuously,
consecutive words will be encoded without an interframe gap.
ENCODER ENABLE must go low by time (5) as shown to
prevent a consecutive word from being encoded. At any time a
low on OI will force both bipolar outputs to a high state but will
not affect the Encoder in any other way.
To Abort the Encoder transmission a positive pulse must be
applied at MR. Any time after or during this pulse, a low-to-high
transition on SCI clears the internal counters and initializes the
Encoder for a new word.
TIMING
SCI
ESC
EE
SS
SD
SDI
BOO
BZO
0
1
2
3
4
5
6
7
15
16 17
18
19
VALID
DON’T CARE
DON’T CARE
15
14
13
12
11 10
1ST HALF 2ND HALF 15
14
13
12
11
SYNC
SYNC
15
14
13 12
11
12
3
3
2
1
0
3
2
1
0
P
3
2
1
0
P
45
FN2952 Rev 3.00
October 1, 2015
Page 4 of 12
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