HB5425161B 查看數據表（PDF） - Elpida Memory, Inc
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HB5425161B Datasheet PDF : 65 Pages
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HM5425161B Series
HM5425801B Series
HM5425401B Series
256M SSTL_2 interface DDR SDRAM
143 MHz/133 MHz/125 MHz/100 MHz
4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank/
16-Mword × 4-bit × 4-bank
E0086H20 (Ver. 2.0)
Jan. 23, 2002
Description
The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM
devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high
speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
Features
• 2.5 V power supply
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 143 MHz/133 MHz/125 MHz/100 MHz (max)
• Data inputs, outputs, and DM are synchronized with DQS
• 4 banks can operate simultaneously and independently
• Burst read/write operation
• Programmable burst length: 2/4/8
Burst read stop capability
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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