HEF4555BT(2018) 查看數據表（PDF） - NXP Semiconductors.
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HEF4555BT Datasheet PDF : 10 Pages
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Nexperia
5. Functional diagram
2 1A0
3 1A1
1 1E
14 2A0
13 2A1
15 2E
DECODER
DECODER
1Y0 4
1Y1 5
1Y2 6
1Y3 7
2Y0 12
2Y1 11
2Y2 10
2Y3 9
Fig. 1. Functional diagram
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6. Pinning information
HEF4555B
1-of-4 decoder/demultiplexer
nY0
nA0
nY1
nA1
nY2
nE
nY3
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Fig. 2. Logic diagram for one decoder/multiplexer
6.1. Pinning
HEF4555B
1E 1
1A0 2
1A1 3
1Y0 4
1Y1 5
1Y2 6
1Y3 7
VSS 8
Fig. 3. Pin configuration SOT109-1 (SO16)
16 VDD
15 2E
14 2A0
13 2A1
12 2Y0
11 2Y1
10 2Y2
9 2Y3
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6.2. Pin description
Table 2. Pin description
Symbol
1A0, 1A1, 2A0, 2A1
1E, 2E
1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3
VDD
VSS
Pin
2, 3, 14, 13
1, 15
4, 5, 6, 7, 12, 11, 10, 9
16
8
Description
address input
enable input (active LOW
output (active HIGH)
supply voltage
ground (GND)
HEF4555B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 15 October 2018
© Nexperia B.V. 2018. All rights reserved
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