HEF4555BT(2018) 查看數據表（PDF） - NXP Semiconductors.
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HEF4555BT Datasheet PDF : 10 Pages
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Nexperia
HEF4555B
1-of-4 decoder/demultiplexer
11.1. Waveforms and test circuit
VDD
nAn, nE input
VM
Fig. 4.
GND
VOH
nYn output
VOL
tPHL
90 %
VM
10 %
tTHL
tPLH
tTLH
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Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Inputs nAn, nE to output nYn propagation delay and nYn output transition time
Table 9. Measurement points
Supply voltage
VDD
5 V to 15 V
Input
VM
0.5VDD
Output
VM
0.5VDD
Fig. 5.
VI
negative
pulse
0V
90 %
VM
10 %
tW
90 %
VM
10 %
tf
tr
VDD
VI
positive
pulse
0V
10 %
tr
90 %
VM
tf
90 %
VI
G
VO
DUT
VM
RT
CL
10 %
tW
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Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
5 V to 15 V
Input
VI
VDD
tr = tf
≤ 20 ns
Load
CL
50 pF
HEF4555B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 15 October 2018
© Nexperia B.V. 2018. All rights reserved
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