HFBR-5208AEMZ 查看數據表（PDF） - Avago Technologies
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HFBR-5208AEMZ
Avago Technologies
HFBR-5208AEMZ Datasheet PDF : 17 Pages
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Reference Design
Avago has developed a reference design for multimode
ATM-SONET/SDH applications shown in Figure 6. This ref-
erence design uses a Vitesse Semiconductor Inc.’s VSC8117
clock recovery/clock generation/serializer/deserializer
integrated circuit and a PMC-Sierra Inc. PM5355 framer
IC. Application Note 1178 documents the design, layout,
testing and performance of this reference design. Gerber
files, schematic and application note are available from
the Avago Fiber-Optics Components’ web site at the URL
of http://www.avagotech.com.
20.32
(0.800)
2 x Ø 1.9 ± 0.1
(0.075 ± 0.004)
Operation in -5.2 V Designs
For applications that require -5.2 V dc power supply level
for true ECL logic circuits, the HFBR-5208xxxZ transceiver
can be operated with a VCC = 0 V dc and a VEE = -5.2 V dc.
This transceiver is not specified with an operating, nega-
tive power supply voltage. The potential compromises
that can occur with use of -5.2 V dc power are that the
absolute voltage states for VOH and VOL will be changed
slightly due to the 0.2 V difference in supply levels. Also,
noise immunity may be compromised for the HFBR-
5208xxxZ trans-ceiver because the ground plane is now
the VCC supply point. The suggested power supply filter
circuit shown in the Recommended Circuit Schematic
figure should be located in the VEE paths at the transceiver
supply pins. Direct coupling of the differential data signal
can be done between the HFBR-5208xxxZ transceiver
and the standard ECL circuits. For guaranteed -5.2 V dc
operation, contact your local Avago Component Field
Sales Engineer for assistance.
20.32
(0.800)
9 x Ø 0.8 ± 0.1
(0.032 ± 0.004)
2.54
(0.100)
TOP VIEW
DIM ENS IONS A RE IN M ILLIM ETERS (INC HES )
Figure 5. Recommended Board Layout Pattern
Figure 6. 622.08 Mb/s OC-12 ATM-SONET/SDH Reference Design Board
5
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