HM-6504 查看數據表（PDF） - Intersil
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HM-6504 Datasheet PDF : 8 Pages
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HM-6504
Timing Waveforms (Continued)
A
E
W
D
0
TIME
REFERENCE
(7)
(8)
TAVEL TELAX
ADD VALID
(6)
TEHEL
(11)
(13)
TWLEL TELWH
HIGH-Z
(15)
(17)
TDVEL TELDX
DATA VALID
-1
0
(18) TELEL
(5) TELEH
1
FIGURE 12. EARLY WRITE CYCLE
(7)
TAVEL
NEXT ADD
(6) TEHEL
(11)
TWLEL
(15)
TDVEL
NEXT DATA
HIGH-Z
2
3
4
TIME REFERENCE
E
-1
H
0
1
L
2
3
H
4
INPUTS
W
A
X
X
L
V
X
X
X
X
X
X
L
V
TRUTH TABLE
OUTPUT
D
Q
X
Z
V
Z
X
Z
X
Z
X
Z
V
Z
FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
Write in Progress Internally
Write Completed
Prepare for Next Cycle (Same as - 1)
Cycle Ends, Next Cycle Begins (Same as 0)
The early write cycle is the only cycle where the output is
guaranteed not to become active. On the falling edge of E
(T = 0), the addresses, the write signal, and the data input
are latched in on-chip registers. The logic value of W at the
time E falls, determines the state of the output buffer for that
cycle. Since W is low when E falls, the output buffer is
latched into the high impedance state and will remain in that
state until E returns high (T = 2). For this cycle, the data
input is latched by E going low; therefore, data set-up and
hold times should be referenced to E. When E (T = 2)
returns to the high state, the output buffer and all inputs are
disabled and all signals are unlatched. The device is now
ready for the next cycle.
6-131
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