AK5358B 查看數據表（PDF） - Asahi Kasei Microdevices

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AK5358B

96kHz 24-Bit ΔΣ ADC

Asahi Kasei Microdevices 

[AK5358B]

SWITCHING CHARACTERISTICS

(Ta=-20°C ∼ 85°C; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 5.5V; CL=20pF)

Parameter

Symbol

min

typ

Master Clock Timing

(Note 11)

512fs, 256fs Frequency

fCLK

2.048

Duty cycle

dCLK

40

768fs, 384fs Frequency

fCLK

3.072

Duty cycle

dCLK

40

max

24.576

60

36.864

60

LRCK Frequency

Duty Cycle

Slave mode

Master mode

fs

8

96

45

55

50

Audio Interface Timing

Slave mode

SCLK Period

tSCK

160

SCLK Pulse Width Low

tSCKL

65

Pulse Width High

tSCKH

65

LRCK Edge to SCLK “↑”

(Note 12) tLRSH

30

SCLK “↑” to LRCK Edge

(Note 12) tSHLR

30

LRCK to SDTO (MSB) (Except I2S mode)

tLRS

35

SCLK “↓” to SDTO

tSSD

35

Master mode

SCLK Frequency

fSCK

64fs

SCLK Duty

dSCK

50

SCLK “↓” to LRCK

tMSLR

−20

20

SCLK “↓” to SDTO

tSSD

−20

35

Reset Timing

PDN Pulse Width

(Note 13) tPD

150

PDN “↑” to SDTO valid at Slave Mode (Note 14) tPDV

PDN “↑” to SDTO valid at Master Mode (Note 14) tPDV

4132

4129

Note 11. The AK5358B is reset by more than 13us “L” period of MCLK. The data is output after initializing.

Note 12. SCLK rising edge must not occur at the same time as LRCK edge.

Note 13. The AK5358B can be reset by bringing the PDN pin = “L”.

Note 14. This cycle is the number of LRCK rising edges from the PDN pin = “H”.

Units

MHz

%

MHz

%

kHz

%

%

ns

ns

ns

ns

ns

ns

ns

Hz

%

ns

ns

ns

1/fs

1/fs

MS1155-E-00

-8-

2010/02

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