CXP5086 查看數據表（PDF） - Sony Semiconductor
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CXP5086 Datasheet PDF : 11 Pages
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CXP5084/5086
(2) Serial transfer
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)
Item
Symbol Pin
Condition
Min.
Max.
Unit
Serial transfer clock (SC)
cycle time
Input mode
tKCY
SC
Output mode
tsys/4 + 1.42
tsys
µs
µs
Input mode
tsys/8 + 0.7
µs
Serial transfer clock (SC)
high and low level widths
tKH
tKL
SC
Output mode∗1
tsys/2 – 0.1
µs
Output mode∗2 tsys/2 – 1.6
µs
Serial data input setup time
(against SC ↑)
tSIK
Serial data input hold time
(against SC ↑)
tKSI
High data∗3 output delay time tKSOA
from the SC falling time
tKSOB
SI
SI
SOA
SOB
SC input mode
SC output mode
SC input mode
SC output mode
0.1
0.2
tsys/8 + 0.5
0.1
µs
µs
µs
µs
tsys/8 + 0.5 µs
High data∗4 output delay time tKSOA
from the SC falling time
tKSOB
SOA
SOB
tsys/8 + 1.6 µs
Low data output delay time
from the SC falling time
tKSOA
tKSOB
SOA
SOB
tsys/8 + 0.5 µs
∗1 It is specified when SC pin is selected to the 3-state output by the mask option.
∗2 It is specified when SC pin is selected to the pull-up resistance by the mask option. As the tsys receives
restriction by this item, take notice that it limits the upper limit of the system clock frequency fc.
∗3 It is specified when SOA and PX1/SOB pins are selected to the 3-state output by the mask option.
∗4 It is specified when SOA and PX1/SOB pins are selected to the pull-up resistance by the mask option.
Note 1) In the standard version, tsys = 16/fc
In the high speed version, tsys = 8/fc
Note 2) The load of data output delay time is 50pF + 1TTL.
–8–
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