ADT7468 查看數據表（PDF） - ON Semiconductor
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ADT7468 Datasheet PDF : 81 Pages
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ADT7468
Parameter
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 TO PWM3, XTO
Current Sink, IOL
Output Low Voltage, VOL
High Level Output Current, IOH
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
SMBUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Detect Clock Low Timeout, tTIMEOUT
SCL
tR
tLOW
tHD; STA
tHD; DAT
Min
Typ
Max
Unit Test Conditions/Comments
8.0
0.4
0.1
1.0
0.4
0.1
1.0
2.0
0.4
500
2.0
5.5
0.8
−0.3
0.5
0.75 × VCCP
0.4
−1
1
5
10
4.7
4.7
4.0
4.7
4.0
250
300
15
tF
400
50
50
1000
300
35
mA
V
IOUT = −8.0 mA, VCC = +3.3 V
µA
VOUT = VCC
V
IOUT = −4.0 mA, VCC = +3.3 V
µA
VOUT = VCC
V
V
mV
V
V
V
V
V p-p
Maximum input voltage
Minimum input voltage
V
V
µA
VIN = VCC
µA
VIN = 0
pF
See Figure 2
kHz
ns
µs
µs
µs
µs
µs
ns
µs
ns
ns
ms Can be optionally disabled
tHD; STA
tHIGH
tSU; DAT
tSU; STA
tSU; STO
SDA
tBUF
P
S
S
P
Figure 2. Serial Bus Timing Diagram
Rev. 3 | Page 4 of 81 | www.onsemi.com
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