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SST29EE010 Datasheet PDF : 27 Pages
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1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Write Operation Status Detection
Hardware Data Protection
The 29EE010/29LE010/29VE010 provide two software Noise/Glitch Protection: A WE# or CE# pulse of less than
means to detect the completion of a write cycle, in order
to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ7)
and Toggle Bit (DQ6). The end of write detection mode is
enabled after the rising WE# or CE# whichever occurs
5 ns will not initiate a write cycle.
VCC Power Up/Down Detection: The write operation is
inhibited when VCC is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
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first, which initiates the internal write cycle.
high will inhibit the write operation. This prevents inad-
The actual completion of the nonvolatile write is asyn-
vertent writes during power-up or power-down.
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chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to
prevent spurious rejection, if an erroneous result occurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the write
cycle, otherwise the rejection is valid.
Software Data Protection (SDP)
The 29EE010/29LE010/29VE010 provide the JEDEC
approved optional software data protection scheme for
all data alteration operations, i.e., Write and Chip erase.
With this scheme, any write operation requires the inclu-
sion of a series of three byte-load operations to precede
the data loading operation. The three byte-load se-
quence is used to initiate the write cycle, providing
optimal protection from inadvertent write operations,
e.g., during the system power-up or power-down. The
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Data# Polling (DQ7)
When the 29EE010/29LE010/29VE010 are in the inter-
29EE010/29LE010/29VE010 are shipped with the soft-
ware data protection disabled.
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nal write cycle, any attempt to read DQ7 of the last byte The software protection scheme can be enabled by
loaded during the byte-load cycle will receive the com-
plement of the true data. Once the write cycle is com-
applying a three-byte sequence to the device, during a
page-load cycle (Figures 4 and 5). The device will then
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pleted, DQ7 will show true data. The device is then ready be automatically set into the data protect mode. Any
for the next operation. See Figure 6 for Data# Polling
timing diagram and Figure 15 for a flowchart.
subsequent write operation will require the preceding
three-byte sequence. See Table 4 for the specific soft-
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ware command codes and Figures 4 and 5 for the timing
Toggle Bit (DQ6)
During the internal write cycle, any consecutive attempts
diagrams. To set the device into the unprotected mode,
a six-byte sequence is required. See Table 4 for the
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to read DQ6 will produce alternating 0’s and 1’s, i.e. specific codes and Figure 8 for the timing diagram. If a
toggling between 0 and 1. When the write cycle is write is attempted while SDP is enabled the device will be
completed, the toggling will stop. The device is then
in a non-accessible state for ~ 300 µs. SST recommends
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ready for the next operation. See Figure 7 for Toggle Bit Software Data Protection always be enabled. See Figure
timing diagram and Figure 15 for a flowchart. The initial 16 for flowcharts.
read of the Toggle Bit will typically be a “1”.
The 29EE010/29LE010/29VE010 Software Data Pro-
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Data Protection
The 29EE010/29LE010/29VE010 provide both hard-
ware and software features to protect nonvolatile data
from inadvertent writes.
tection is a global command, protecting (or unprotecting)
all pages in the entire memory array once enabled (or
disabled). Therefore using SDP for a single page write
will enable SDP for the entire array. Single pages by
themselves cannot be SDP enabled or disabled.
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© 1998 Silicon Storage Technology, Inc.
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304-04 12/97
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