SST30VR021-70-E-UH 查看數據表（PDF） - Silicon Storage Technology

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SST30VR021-70-E-UH

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo

Silicon Storage Technology 

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

Data Sheet

TABLE 4: CAPACITANCE (Ta = 25°C, f=1 Mhz)

Parameter

Description

Test Condition

Maximum

CI/O1

CIN1

I/O Pin Capacitance

Input Capacitance

VI/O = 0V

VIN = 0V

8 pF

6 pF

T4.1 380

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

VIHT

INPUT

VIT

REFERENCE POINTS

VOT

OUTPUT

VILT

380 ILL F08.0

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

TO DUT

380 ILL F09.0

FIGURE 3: A TEST LOAD EXAMPLE

TO TESTER

CL

©2001 Silicon Storage Technology, Inc.

4

S71135-02-000 4/01 380

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