SST30VR021-70-E-U1 查看數據表（PDF） - Silicon Storage Technology

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SST30VR021-70-E-U1

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo

Silicon Storage Technology 

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

Data Sheet

Address

Data Out

TRC

TAA

TOH

Previous Data Valid

Data Valid

380 ILL F04.0

FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE# = RAMCS# = VIL, WE# = VIH)

TRC

Address

OE#

TAA

TOE

TOHZ(1)

RAMCS#

TCO

THZ (1,2)

Data Out

High-Z

TLZ(2)

Data Valid

TOH

Notes:

1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition

and are referenced to the VOH or VOL.

2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given

device and from device to device.

3. WE# is high for Read cycle.

4. Address valid prior to coincidence with RAMCS# transition low.

380 ILL F05.0

FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE# OR RAMCS# CONTROLLED)

©2001 Silicon Storage Technology, Inc.

8

S71135-02-000 4/01 380

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