BUK553-48C 查看數據表（PDF） - Philips Electronics

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BUK553-48C

PowerMOS transistor Voltage clamped logic level FET

Philips Electronics 

Philips Semiconductors

PowerMOS transistor

Voltage clamped logic level FET

Product specification

BUK553-48C

a

2.0

Normalised RDS(ON) = f(Tj)

1.5

1.0

0.5

0

-60

-20

20

60

100

140

180

Tj / C

Fig.11. Normalised drain-source on-state resistance.

a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 5 V

ID / A

1E-01

SUB-THRESHOLD CONDUCTION

1E-02

1E-03

2%

typ

98 %

1E-04

1E-05

1E-06

0

0.4

0.8

1.2

1.6

2

2.4

VGS / V

Fig.12. Sub-threshold drain current.

ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS

C / pF

2000

1000

500

BUK5Y3-48C

Ciss

200

Coss

100

Crss

50

0.01

0.1

1

VDS / V

10

100

Fig.13. Typical capacitances, Ciss, Coss, Crss.

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

VGS(TO) / V

2

1

max.

typ.

min.

0

-60

-20

20

60

100

140

180

Tj / C

Fig.14. Gate threshold voltage.

VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS

IS / A

40

Tmb / degC =

150

30 25

-55

20

BUK5Y3-48C

10

0

0

0.5

1

1.5

VSDS / V

Fig.15. Typical reverse diode current.

IF = f(VSDS); conditions: VGS = 0 V; parameter Tj

VGS / V

7

6

VDD / V = 12

BUK5Y3-48C

30

5

4

3

2

1

0

0

5

10

15

20

QG / nC

Fig.16. Typical turn-on gate-charge characteristics.

VGS = f(QG); conditions: ID = 10 A; parameter VDS

August 1994

5

Rev 1.000

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