LCX007CL 查看數據表（PDF） - Sony Semiconductor
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LCX007CL Datasheet PDF : 24 Pages
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LCX007CL
2. LCD Panel Operations
[Description of basic operations]
The basic operations of the LCD panel are shown below based on the wide-display mode.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 480 gate lines sequentially in every horizontal scanning period.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 1068.5 signal electrodes sequentially in a single horizontal scanning period.
• Vertical and horizontal shift registers address one pixel, and then turn on Thin Film Transistors (TFTs; two
TFTs) to apply a video signal to the dot. The same procedures lead to the entire 480 x 1068.5 dots to display
a picture in a single vertical scanning period.
• The LCD pixel dots are arranged in a delta pattern, where the dots connected to the identical signal line is
positioned with 1.5-dot offset against an adjacent horizontal line. Horizontal Start Pulse (HST) is generated
with 1.5-bit offset between the horizontal lines to regulate the above offset. HCK and sample-hold (S/H)
pulses follow the same 1.5-bit offset scheme.
• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the VVDD potential drops to approximately 9.5V. This pin shall be
grounded when not in use.
• The video signal shall be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal display cycle are shown below:
(1) Vertical display cycle
VD
VST
VCK
1
2
480
Vertical display cycle 480H
(2) Horizontal display cycle (16:9)
BLK
HST
HCK1
HCK2
(3) Horizontal display cycle (4:3)
123 45 6
Horizontal display cycle
356
357
BLK
HST
HCK1
HCK2
12 3456
267
268
Horizontal display cycle
– 18 –
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