CXD1961AQ 查看數據表（PDF） - Sony Semiconductor
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CXD1961AQ Datasheet PDF : 33 Pages
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CXD1961AQ
Sub address 08 (hex)
Read
DC_OFST DC offset level of A to D converter
OFI3 to OFI0
DC offset value of the I channel A/D converter.
OFI3: Sign
OFQ3 to OFQ0
OFQ3: Sign
DC offset value of the Q channel A/D converter.
In both cases, the value is depend on the operation mode.
MOFST (reg. IE)
0
1
Operating mode
OFI [3:0] / OFQ [3:0]
Offset bias mode Current offset value.
Offset cancel mode
Compensation value for each
A/D converter.
Refer to the explanation of register 1E (hex).
Sub address 09 (hex)-A
Read
FLAG
Status Flag
Register 09 (hex) has an irregular structure. Two register -A and -B are correspond to the sub-address 09
(hex). When SEL09 of the register 0E (hex) is 0, register 09 (hex)-A is selected, else register 09 (hex)-B is
selected.
VCOLK
This bit become 0 in case of abnormal oscillation of embedded VCO.
NAK
FSYNC
(Tuner interface I2C bus mode)
This bit becomes 1 in case of no acknowledge from the tuner PLL.
This bit becomes 1 iwhen Frame synchronization is achieved.
VSYNC
This bit becomes 1 when the punctured mapping synchronization is achieved.
QSYNC
This bit becomes 1 when carrier lock is achieved.
ID
This bit is always 1.
Sub address 09 (hex)-B
Sub address 0A (hex)
Read
Read
CM_LOW
CM_UPR
Constellation Monitor
Constellation Monitor
These registers can be access when SEL09 of register 0E (hex) is 1.
CM15 to CM0
(MSB) (LSB)
Monitor value of the QPSK constellation. This value depends on the AGC
reference (reg. 21 (hex)). Refer to Fig.1.
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