CXD1961AQ 查看數據表（PDF） - Sony Semiconductor

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CXD1961AQ

DVB-S Frontend IC (QPSK demodulation + FEC)

Sony Semiconductor 

CXD1961AQ

Block Diagram

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

AVS0 1

RB0 2

VDD0 3

VSS0 4

TEST1 5

TEST2 6

TEST3 7

TEST4 8

NC 9

VDD1 10

VSS1 11

SDAT/SCL 12

SCLK 13

SEN/SDA 14

VDD2 15

VSS2 16

TCK 17

TMS 18

TEST6 19

TEST7 20

CK8OUT 21

RESET 22

TE 23

VDD3 24

VSS3 25

PKTCLK 26

BYTCLK 27

PKTERR 28

DATA0 29

DATA1 30

analog I/O

Sampling

2ch ADC

Clock

VCO

PLL

QPSK

Demodulator

Viterbi Decoder

NCO

De-interleaver

Reed-Solomon

Decoder

Energy Dispersal

decoded data

& clock

CPU I/F

I2C bus

80 VDD9

79 CR7

78 CR6

77 CR5

76 CR4

75 VSS8

74 VDD8

73 CR3

72 CR2

71 CR1

70 CR0

69 CKV

68 AGCPWM

67 VSS7

66 VDD7

65 VCK

64 VDT

63 XI

62 XO

61 AVS3

60 AVD3

59 SDA

58 SCL

57 TEST22

56 TEST21

55 TEST20

54 VSS6

53 VDD6

52 TEST19

51 TEST18

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Typical Block Diagram

LNB

SAW

VCO

PLL

Reference

Amp

I/Q

detector

LPF

LPF

479.5MHz

90°

OSC

Micro Controller

–2–

QPSK + FEC

SONY

CXD1961AQ

Data

Clock

LPF

Crystal

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