CXD3511AQ
Parallel I/F Block AC Characteristics (Topr = –20 to +75°C, VDD1 = 2.5 ± 0.2V, VDD2 = 3.3 ± 0.3V, VSS = 0V)
Item
PCTL setup time with respect to rise of PCLK
PCTL hold time with respect to rise of PCLK
PDAT[9:0] setup time with respect to rise of PCLK
PDAT[9:0] hold time with respect to rise of PCLK
PCLK pulse width
Symbol Min. Typ. Max.
tcs
8T∗5
—
—
tch
8T
—
—
tds
4T
—
—
tdh
4T
—
—
tw
4T
—
—
∗5 T: Master clock (CLKP, CLKN, CLKC) period [ns]
Timing Definition
PCTL
PCLK
PDAT[9:0]
tcs
50%
tw
50%
tds
50%
tch
tw
50%
tdh
50%
50%
VDD2
VSS
VDD2
VSS
VDD2
VSS
– 14 –