CXD3511AQ 查看數據表（PDF） - Sony Semiconductor

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CXD3511AQ

Digital Signal Driver/Timing Generator

Sony Semiconductor 

3. Description of DSD Block Signal Processing Functions

The DSD block signal processing flow is shown below.

R, G, B IN

Data path

switch

Pre gain

Pre bright

User gain User bright

Sub gain

Sub bright

Black

frame

Mute 1

YS, YM, R, G, B OSD

Pattern

generator

OSD

Gamma

correction

Color shading

correction

CXD3511AQ

Selectable

delay line

Mute 2

Limiter

Post gain

Post bright

Ghost

cancel

Cycle

offset

R, G, B OUT

The various signal processing functions are described below. Note that the coefficients used for each

arithmetic operation are set through the parallel I/F block. See the individual descriptions of each parallel I/F

block item for a detailed description of the parallel I/F block.

(a) Data path switch block

This block can switch the path of the data input to ports 1 and 2. The setting is as follows.

Select signal: 1 = Path switched, 0 = Path not switched (Set independently for R, G and B)

Select signal (R, G, B_DAT_SW)

8

Input (port 1)

8

Input (port 2)

Selector

8

Output (port 1)

Selector

8

Output (port 2)

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