FPAL15SM60 查看數據表（PDF） - Fairchild Semiconductor
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FPAL15SM60 Datasheet PDF : 17 Pages
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Recommended Operating Conditions
Item
Supply Voltage
Control Supply Voltage
High-side Bias Voltage
Blanking Time for Preventing
Arm-short
PWM Input Signal
Input ON Threshold Voltage
Input OFF Threshold Voltage
Symbol
Condition
VPN
VCC
VBS
tdead
Applied between P - N
Applied between VCC(H) - COM, VCC(L) - COM
Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
For Each Input Signal
Min.
-
13.5
13.5
Value
Typ.
300
15
15
Max.
400
16.5
16.5
3
-
-
Unit
V
V
V
us
fPWM
VIN(ON)
VIN(OFF)
TC ≤ 100°C, TJ ≤ 125°C
Applied between UIN,VIN, WIN - COM
Applied between UIN,VIN, WIN - COM
-
7
- kHz
0 ~ 0.65
V
4 ~ 5.5
V
ICs Internal Structure and Input/Output Conditions
15V Line
5V Line
RP
CBP15
CPH
5V Line
RP
RPF
CPL
CPF
CFOD
RBS
DBS
CBS
CBSC
VCC(UH,VH,WH)
IN(UH,VH,WH)
COM
LEVEL
SHIFT
PULSE
GENERATOR
UV
DETECT
PULSE
FILTER
R
R
SQ
HVIC
VB(UH,VH,WH)
VS(UH,VH,WH)
VCC(L)
UV
DETECT
BANDGAP
REFERENCE
IN(UL,VL,WL)
PULSE
GENERATOR
(HYSTERISIS)
VFO
CFOD
FAULT OUTPUT
DURATION
TIME
DELAY
UV
LATCH_UP
LVIC
UV
PROTECTION
SC
PROTECTION
BUFFER
SOFT_OFF
CONTROL
SC
LATCH_UP
TIME
DELAY
SC
DETECTION
OUTPUT
(UL,VL,WL)
CSC
RF
RSC
P
U,V,W
N
Note
1. One LVIC drives three Sense-IGBTs and can do short-circuit current protection also. Three sense emitters are commonly connected to RSC terminal to detect
short-circuit current. Low-side part of the inverter consists of three sense-IGBTs
2. One HVIC drives one normal-IGBT. High-side part of the inverter consists of three normal-IGBTs
3. Each IC has under voltage detection and protection function.
4. The logic input is compatible with standard CMOS or LSTTL outputs.
5. RPCP coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each
SPM gating input pin.
6. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
Fig. 11.
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
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