EFM32LG 查看數據表（PDF） - Silicon Laboratories

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EFM32LG

EFM32 Leopard Gecko Family

Silicon Laboratories 

EFM32LG Data Sheet

Feature List

1. Feature List

• ARM Cortex-M3 CPU platform

• High Performance 32-bit processor @ up to 48 MHz

• Memory Protection Unit

• Wake-up Interrupt Controller

• SysTick System Timer

• Flexible Energy Management System

• 20 nA @ 3 V Shutoff Mode

• 0.4 µA @ 3 V Shutoff Mode with RTC

• 0.65 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention

• 0.95 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and

CPU retention

• 63 µA/MHz @ 3 V Sleep Mode

• 211 µA/MHz @ 3 V Run Mode, with code executed from flash

• 256/128/64 kB Flash

• 32 kB RAM

• Up to 93 General Purpose I/O pins

• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength

• Configurable peripheral I/O locations

• 16 asynchronous external interrupts

• Output state retention and wake-up from Shutoff Mode

• 12 Channel DMA Controller

• 12 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling

• Hardware AES with 128/256-bit keys in 54/75 cycles

• Timers/Counters

• 4× 16-bit Timer/Counter

• 4×3 Compare/Capture/PWM channels

• Dead-Time Insertion on TIMER0

• 16-bit Low Energy Timer

• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter

• 3× 16/8-bit Pulse Counter

• Watchdog Timer with dedicated RC oscillator @ 50 nA

• Integrated LCD Controller for up to 8×36 segments

• Voltage boost, adjustable contrast and autonomous animation

• Backup Power Domain

• RTC and retention registers in a separate power domain, available in all energy modes

• Operation from backup battery when main power drains out

• External Bus Interface for up to 4x256 MB of external memory mapped space

• TFT Controller with Direct Drive

• Communication interfaces

• Up to 3× Universal Synchronous/Asynchronous Receiver/Transmitter

• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S

• 2× Universal Asynchronous Receiver/Transmitter

• 2× Low Energy UART

• Autonomous operation with DMA in Deep Sleep Mode

• 2× I2C Interface with SMBus support

• Address recognition in Stop Mode

• Universal Serial Bus (USB) with Host & OTG support

• Fully USB 2.0 compliant

• On-chip PHY and embedded 5V to 3.3V regulator

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