GA1085MC 查看數據表（PDF） - TriQuint Semiconductor

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GA1085MC

11-Output Configurable Clock Buffer

TriQuint Semiconductor 

GA1085

AC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C)

Symbol

tCPWH

tCPWL

tIR

Input Clock (REFCLK)

CLK pulse width HIGH

CLK pulse width LOW

Input rise time (0.8 V – 2.0 V)

Output Clocks (Q0–Q10)

Test Conditions (Figure 3)1

Figure 4

Figure 4

Min Typ Max Unit

3 --- — ns

3 --- — ns

— — 2.0 ns

tOR, tOF

tPD2

tSKEW13

tSKEW23

tSKEW33

tSKEW43

tCYC4

tJP5

tJR5

tSYNC6

Rise/fall time (0.8 V–2.0 V)

CLK Î to FBIN Î (GA1085-MC1000)

Rise–rise, fall–fall (within group)

Rise–rise, fall–fall

(group-to-group, aligned)

Rise–rise, fall–fall

(group-to-group, non-aligned)

Rise–fall, fall–rise

Duty-cycle Variation

Period-to-Period Jitter

Random Jitter

Synchronization Time

Figure 4

350 — 1400 ps

Figure 4

–1350–350 +650 ps

Figure 5

— 60 150 ps

Figure 6

— 75 350 ps

(skew2 takes into account skew1)

Figure 7

— — 650 ps

(skew3 takes into account skew1, skew2)

Figure 8

— — 1200 ps

(skew4 takes into account skew3)

Figure 4

–1000 0 +1000 ps

Figure 4

— 80 200 ps

Figure 4

— 190 400 ps

— 10 500 µs

Notes:

1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).

2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty

cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.

3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.

4. This specification represents the deviation from 50/50 on the outputs.

5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock.

tJP is the jitter on the output with respect to the output’s previous rising edge.

6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and

a connection from one of the outputs to FBIN.

Figure 3. AC Test Circuit

+5 V

R1

Z

R2

+5 V

R1

Z

R2

Notes:

R1 = 160 Ω

R2 = 71 Ω

Y+Z=X

Y

FBIN Q0

Q1

Q2

•

•

•

•

CLK Q10

50 Ω

X

•

•

•

•

+5 V

R1 +5 V

R2 R1

R2

+5 V

R1

R2

For additional information and latest specifications, see our website: www.triquint.com

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