CS8952T 查看數據表（PDF） - Cirrus Logic

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CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Cirrus Logic 

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

MII Interface Pins

COL/PHYAD0 - Collision Detect/PHY Address 0. Input/Tri-State Output, Pin 48.

Asserted active-high to indicate a collision on the medium during half-duplex operation. In

full-duplex operation, COL is undefined and should be ignored. When configured for 10 Mb/s

operation, COL is also used to indicate a Signal Quality Error (SQE) condition.

At power-up or at reset, the logic value on this pin is latched into bit 0 of the PHY Address

field of the Self Status Register (address 19h). This pin includes a weak internal pull-down

(~ 20 KΩ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor.

NOTE: Silicon revisions A and B included a weak internal pull-up rather than a pull-down.

CRS/PHYAD2 - Carrier Sense/PHY Address 2. Input/Tri-State Output, Pin 49.

The operation of CRS is controlled by the REPEATER pin as follows:

REPEATER pin

high

low

low

DUPLEX mode

don’t care

full duplex

half duplex

CRS Indicates

receive activity only

receive activity only

receive or transmit activity

At power-up or at reset, the logic value of this pin is latched into bit 2 of the PHY Address

Field of the Self Status Register (address 19h). This pin includes a weak internal pull-down

(> 20 KΩ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor.

MDC - Management Data Clock. Input, Pin 28.

Input clock used to transfer serial data on MDIO. The maximum clock rate is 16.67 MHz. This

clock may be asynchronous to RX_CLK and TX_CLK.

MDIO - Management Data Input/Output. Bi-Directional, Pin 27.

Bi-directional signal used to transfer management data between the CS8952T and the Ethernet

controller.

In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin

should be pulled high during power-up or reset, and the MDIO pin should have an external

1.5 KΩ pull-up resistor.

MII_IRQ - MII Interrupt. Open Drain Output, Pin 26.

Asserted low to indicate the status corresponding to one of the unmasked interrupt status bits in

the Interrupt Status Register (address 11h) has changed. It will remain low until the ISR is read,

clearing all status bits.

This open drain pin requires a 4.7 kΩ pull-up resistor.

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

DS206TPP2

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