FT8010 查看數據表（PDF） - ON Semiconductor

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FT8010

Reset Timer with Configurable Delay Time

ON Semiconductor 

Physical Dimensions

0.10 C

2X

1.40

AB

0.663

1.70

(9X)

0.563

PIN#1 IDENT

TOP VIEW

1.80

0.10 C

2X

0.10 C 0.55 MAX. (0.15)

1

0.40

2.10

(10X)0.225

RECOMMENDED

LAND PATTERN

0.08 C

0.05

0.00

SEATING C

PLANE

1.45

9X

0.55

0.45

SIDE VIEW

00..3455 (9X)

3

DETAIL A

0.40

6

1

PIN#1 IDENT

10

00..1255(10X)

BOTTOM VIEW

0.10 C A B

0.05 C

0.55

0.45

PACKAGE

EDGE

0.40

1.85

(10X) 0.225

OPTIONAL MINIMIAL

TOE LAND PATTERN

NOTES:

A. PACKAGE DOES NOT CONFORM TO

ANY JEDEC STANDARD.

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

D. LAND PATTERN RECOMMENDATION IS

BASED ON FSC DESIGN ONLY.

E. DRAWING FILENAME: MKT-UMLP10Arev5.

F. FAIRCHILD SEMICONDUCTOR.

45°

0.25

0.15 DETAIL A

SCALE : 2X

LEAD

OPTION 1

SCALE : 2X

LEAD

OPTION 2

SCALE : 2X

Figure 8. 10-Lead, Ultrathin MLP, 1.4 x 1.8 x 0.55 mm Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

© 2009 Fairchild Semiconductor Corporation

FT8010 • Rev. 1.0.8

11

www.fairchildsemi.com

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