FT8010 查看數據表（PDF） - ON Semiconductor
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FT8010 Datasheet PDF : 15 Pages
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Physical Dimensions (Continued)
0.10 C
2X
2.00
A
B
PIN1
IDENT
TOP VIEW
2.00
0.10 C
2X
0.80 MAX
0.10 C
0.08 C 0.05
0.00
SEATING
PLANE
SIDE VIEW
(0.20)
C
0.25
0.15
8X
A
1
4
0.65
0.45
8X
PIN 1
IDENT
8
0.50
0.40 MAX
0.10
5
0.05
1.35 MAX
CAB
C
BOTTOM VIEW
0.90
1.80
TOP LAYER
CU KEEP
OUT AREA
E
(0.90) 8X
0.50
(0.25) 8X
OPTION #1: NO CENTER PAD
(1.35)
0.90
1.80
0.50
(0.35)
(0.90) 8X
(0.25) 8X
OPTION #2: WITH CENTER PAD
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
NOTES:
A. PACKAGE CONFORMS TO JEDEC MO-229,
VARIATION W2020D EXCEPT WHERE NOTED.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION BASED
ON PCB MATRIX CALCULATOR V2009.
E. IF CENTER PAD IS NOT SOLDERED TO, NO
EXPOSED METAL IS ALLOWED IN THE TOP
LAYER OF THE BOARD IN THE AREA SHOWN.
F. DRAWING FILENAME: MKT-MLP08Rrev2.
Figure 9. 8-Lead, Molded Leadless Package (MLP), 2.0 x 2.0 x 0.8 mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
12
www.fairchildsemi.com
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