ISPLSI1032EA 查看數據表（PDF） - Lattice Semiconductor

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ISPLSI1032EA

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 1032EA

Internal Timing Parameters1

PARAM. #

DESCRIPTION

Outputs

tob

50 Output Buffer Delay

tsl

51 Output Buffer Delay, Slew Limited Adder

toen

52 I/O Cell OE to Output Enabled

todis

53 I/O Cell OE to Output Disabled

tgoe

54 Global OE

Clocks

tgy0

55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk)

tgy1/2 56 Clock Delay, Y1 or Y2 to Global GLB Clock Line

tgcp

57 Clock Delay, Clock GLB to Global GLB Clock Line

tioy2/3 58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

tiocp

59 Clock Delay, Clock GLB to I/O Cell Global Clock Line

Global Reset

tgr

60 Global Reset to GLB and I/O Registers

1. Internal Timing Parameters are not tested and are for reference only.

-200

-170

UNITS

MIN. MAX. MIN. MAX.

— 0.9 — 1.1 ns

— 5.0 — 5.0 ns

— 3.1 — 3.5 ns

— 3.1 — 3.5 ns

— 1.4 — 2.9 ns

0.9 0.9 0.9 0.9 ns

0.9 0.9 0.9 0.9 ns

0.8 1.8 0.8 1.8 ns

0.0 0.0 0.0 0.0 ns

0.8 2.8 0.8 2.8 ns

— 0.0

— 0.4 ns

Table 2-0037A/1032EA

v.2.4

9

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