TR8100 查看數據表（PDF） - Murata Manufacturing

零件编号

产品描述 (功能)

生产厂家

TR8100

916.50 MHz Hybrid Transceiver

Murata Manufacturing 

Pin

Name

Description

18

CFGCLK In 3G control mode, pulses on CFGCLK are used to clock configuration data into and out of the radio through

CFGDAT (Pin 17). When writing through CFGDAT, a data bit is clocked into the radio on the rising edge of a

CFGCLK pulse. When reading through CFGDAT, data is output on the rising edge of the CFGCLK pulse and is

stable for reading on the falling edge of the CFGCLK. CFGCLK is inactive when the CFG (Pin 19) is set to logic

0. See Page 6 for details of 2G default control mode operation of this pin.

19

CFG CFG controls the operation of the CFGDAT (Pin 17) and CFGCLK (Pin 18) pins. If CFG is held at logic 0 when

the radio is powered on, radio operation defaults to 2G control mode as explained on Page 6. Radio operation

is switched to 3G serial control mode the first time CFG is set to logic 1. CFG must be set to a logic 1 before data

can be clocked into or out of CFGDAT by CFGCLK. CFGDAT is inactive when the CFG (Pin 19) is set to logic

0. Setting CFG to a logic 1 will also switch the radio from sleep mode to active mode.

20

RFIO RFIO is the RF input/output pin. This pin is connected directly to the SAW filter transducer. Antennas presenting

an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series

matching coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two

or three components. For some impedances, two inductors and a capacitor will be required. A DC path from

RFIO to ground is required for ESD protection.

©2010-2015 by Murata Electronics N.A., Inc.

TR8100 (R) 4/24/15

Page 10 of 15

www.murata.com

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