TR8100 查看數據表（PDF） - Murata Manufacturing

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TR8100

916.50 MHz Hybrid Transceiver

Murata Manufacturing 

LOSyn Bit 7 - This bit is only used in product testing. It should

always be set to 0 for normal operation. The power-on default

value of this bit is 0.

LOSyn Bits 6, 5, 4, 3, 2, 1, 0 -These bits have no function in the

TR8100-1 and can be written as either a logic 1 or a logic 0.

Note that data to/from the configuration registers is clocked in/out

most significant bit first (MSB). See the Control Register Read/

Write Detail and Control Register Read/Write Timing Drawings for

additional details.

Receiver Turn-On Timing

The maximum time tPR required for the receive function to become

operational at turn-on is influenced by two factors. All receiver

circuitry will be operational 1 ms after the supply voltage reaches

2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC

stabilized in 4 time constants (4*tBBC). The total turn-on time to

stable receiver operation for a 10 ms power supply rise time is:

tPR =15 ms +4*tBBC

Pin Descriptions

Receiver Wake-Up Timing

The maximum transition time tSR from the sleep mode to the

receive mode is 4*tBBC, where tBBC is the BBOUT-CMPIN

coupling-capacitor time constant. When the operating temperature

is limited to 60°C, the time required to switch from sleep to receive

is dramatically less for short sleep times, as less charge leaks

away from the BBOUT-CMPIN coupling capacitor.

AGC Timing

The maximum AGC engage time tAGC is 5 µs after the reception

of a -30 dBm RF signal with a 1 µs envelope rise time.

Peak Detector Timing

The Peak Detector attack time constant is set by the value of the

capacitor at the PKDET pin. The attack time tPKA =CPKD/4167,

where tPKA is in µs and CPKD is in pF. The Peak Detector decay

time constanttPKD = 1000*tPKA.

Pin

Name

Description

1

GND1 GND1 is the RF ground pin.

2

VCC1 VCC1 is a positive supply voltage pin. VCC1 is decoupled with a ferrite bead and bypassed by an RF capacitor.

3

VCC3 VCC3 is a positive supply voltage pin. VCC3 is bypassed by an RF capacitor.

4

PKDET This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector attack and

decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordinated with the

base-band time constant. For a given base-band capacitor CBBO , the capacitor value CPKD is:

CPKD = 2.0* CBBO , where CBBO and CPKD are in pF

A ±10% ceramic capacitor should be used at this pin. This time constant will vary between tPKA and 1.5* tPKA with variations

in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays through a 200 K

load. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release function. The peak detector

capacitor is discharged in the receiver power-down (sleep) mode and in the transmit modes.

5

BBOUT BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor CBBO for internal

data slicer operation. The time constant tBBC for this connection is:

tBBC = 0.1CBBO , where tBBC is in µs and CBBO is in pF

A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between tBBC and

1.8*tBBC with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will depend

on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide.

CBBO = 11.2*SPMAX, where SPMAX is the maximum signal pulse width in µs and CBBO is in pF

The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output imped-

ance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes

about 10 mV/dB, with a peak-to-peak signal level of up to 450 mV. The signal at BBOUT is riding on a 1.5 Vdc value that var-

ies somewhat with supply voltage and temperature, so it should be coupled through a capacitor to an external load. A load

impedance of 50 K to 500 K in parallel with no more than 10 pF is recommended. When an external data recovery process is

used with AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling

capacitors. The AGC reset function is driven by the signal applied to CMPIN. When the transceiver is in power-down (sleep)

or in a transmit mode, the output impedance of this pin becomes very high, preserving the charge on the coupling capacitor.

6

CMPIN This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance of

this pin is 100 K.

7

RXDATA RXDATA is the receiver data output pin. It is a CMOS output. The signal on this pin can come from one of two sources. The

default source is directly from the output of the data slicer circuit. The alternate source is from the radio’s internal data and

clock recovery circuit. When the internal data and clock recovery circuit is used, the signal on RXDATA is switched from the

output of the data slicer to the output of the data and clock recovery circuit when a packet start symbol is detected. Each

recovered data bit is then output on the rising edge of a RXDCLK pulse (Pin 14), and is stable for reading on the falling edge

of the RXDCLK pulse.

©2010-2015 by Murata Electronics N.A., Inc.

TR8100 (R) 4/24/15

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