TR8100 查看數據表（PDF） - Murata Manufacturing
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TR8100 Datasheet PDF : 15 Pages
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Pin
Name
Description
8
TXMOD The transmitter RF output voltage is proportional to the input current to this pin. A resistor in series with the TXMOD input is
normally used to adjust the peak transmitter output. Full transmitter power (10 mW) requires about 315 µA of drive current.
The transmitter output power PO for a 3 Vdc supply voltage is approximately:
PO = 101*(ITXM)2, where PO is in mW and the modulation current ITXM is in mA
The practical power control range is 10 to -50 dBm. A ±5% TXMOD resistor value is recommended. Internally, this pin is con-
nected to the base of a bipolar transistor with a small emitter resistor. The voltage at the TXMOD input pin is about 0.87 volt
with 315 uA of drive current. This pin accepts analog modulation and can be driven with either logic level data pulses
(unshaped) or shaped data pulses.
9
LPFADJ This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor RLPF between this pin and
ground. The resistor value can range from 510 K to 3 K, providing a filter 3 dB bandwidth fLPF from 5 to 600 kHz. The resistor
value is determined by:
RLPF = (0.0006*fLPF) -1.069 where RLPF is in kilohms, and fLPF is in kHz
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dBfilter bandwidth between fLPF and 1.3* fLPF
with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response.
10
GND2 GND2 is an IC ground pin.
11
RREF RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%
resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less
than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less
that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF.
12
THLD2 THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 Kresistor RTH2
between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak detector value
(increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB below peak. The THLD2
resistor value is given by:
RTH2 = 1.5*V, where RTH2 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the dB-below-peak
data slicer operation.
13
THLD1 The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The threshold is
increased by increasing the resistor value. Connecting this pin directly to RREF provides zero theshold. The value of the
resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the acceptable range for the resistor is 0
to 200K, providing a THLD1 range of 0 to 112 mV. The resistor value is given by:
For thresholds 0 ≤ V ≤ 30mV :
RTH1 = 3.81*V -14.28, where RTH1 is in kilohms and the threshold V is in mV.
For thresholds 31mV ≤ V ≤ 112mV :
RTH1 = 1.22*V +63.36, where RTH1 is in kilohms and the threshold V is in mV.
For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 100K. The resistor value is given by:
RTH1 = 2.22*V, where RTH1 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required for proper
AGC operation. The minimum value recommended is 20K.
14
RXCLK RXDCLK is the clock output from the data and clock recovery circuit. RXDCLK is a CMOS output. When the radio’s internal
data and clock recovery circuit is not used, RXDCLK is a steady low value. When the internal data and clock recovery is
used, RXDCLK is low until a packet start symbol is detected at the output of the data slicer. Each bit following the start sym-
bol is output at RXDATA on the rising edge of a RXDCLK pulse, and is stable for reading on the falling edge of the RXDCLK
pulse. Once RXDCLK is activated by the detection of a start symbol, it remains active until CFG0 Bit 0 is set to 0. Normally
RXDCLK is reset by the host processor as soon as a packet is received.
15
GND3 GND3 is an IC ground pin.
16
VCC2 VCC2 is a positive supply voltage pin. Pin 16 must be bypassed with an RF capacitor, and must also be by passed with a 1
µF tantalum or electrolytic capacitor.
17
CFGDAT In 3G control mode, CFGDAT is a bi-directional CMOS logic pin. When CFG (Pin 19) is set to a logic 1, configuration data
can be clocked into or out of the radio’s configuration registers through CFGDAT using CFGCLK (Pin 18). Data clocked into
CFGDAT is transferred to a control register each time a group of 8 bits is received (see Figure 4). Pulses on CFGCLK are
used to clock configuration data into and out of the radio through CFGDAT (Pin 17). When writing through CFGDAT, a data
bit is clocked into the radio on the rising edge of a CFGCLK pulse. When reading through CFGDAT, data is output on the ris-
ing edge of the CFGCLK pulse and is stable for reading on the falling edge of the CFGCLK. CFGCLK is inactive when the
CFG (Pin 19) is set at a logic 0. See Page 6 for details of 2G default control mode operation of this pin.
©2010-2015 by Murata Electronics N.A., Inc.
TR8100 (R) 4/24/15
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