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LH28F004SUT-NC80 查看數據表(PDF) - Sharp Electronics

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LH28F004SUT-NC80
Sharp
Sharp Electronics Sharp
LH28F004SUT-NC80 Datasheet PDF : 31 Pages
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LH28F004SU-NC
4M (512K × 8) Flash Memory
INTRODUCTION
Sharp’s LH28F004SU-NC 4M Flash Memory is a
revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and
communication products. With innovative capabilities,
5 V single voltage operation and very high read/write
performance, the LH28F004SU-NC is also the ideal
choice for designing embedded mass storage flash
memory systems.
The LH28F004SU-NC’s independently lockable 32
symmetrical blocked architecture (16K each) extended
cycling, low power operation, very fast write and read
performance and selective block locking provide a highly
flexible memory component suitable for cellular phone,
facsilime, game, PC, printer and handy terminal. The
LH28F004SU-NC’s single power supply operation en-
ables the design of memory cards which can be read/
written in 5.0 V systems. Its x8 architecture allows the
optimization of memory to processor interface.The flex-
ible block locking option enables bundling of executable
application software in a Resident Flash Array or
memory card. Manufactured on Sharp’s 0.45 µm
ETOX™ process technology, the LH28F004SU-NC is
the most cost-effective, high-density 5.0V flash memory.
DESCRIPTION
The LH28F004SU-NC is a high performance 4M
(4,194,304 bit) block erasable non-volatile random
access memory organized as 512K × 8. The
LH28F004SU-NC includes thirty-two 16K (16,384)
blocks. A chip memory map is shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F004SU-NC:
5 V Read, Write/Erase Operation (5 V VCC,VPP)
Low Power Capability
Improved Write Performance
Dedicated Block Write/Erase Protection
Command-Controlled Memory Protection
Set/Reset Capability
The LH28F004SU-NC will be available in a 40-pin,
1.2 mm thick × 10 mm × 20 mm TSOP (Type I) pack-
age.This form factor and pinout allow for very high board
layout densities.
A Command User Interface (CUI) serves as the sys-
tem interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
Software Locking of Memory Blocks
Memory Protection Set/Reset Capability
Two-Byte Serial Writes in 8-bit Systems
Erase All Unlocked Blocks
Writing of memory data is performed typically within
13 µs. A Block Erase operation erases one of the 32
blocks in typically 0.6 seconds, independent of the other
blocks.
LH28F004SU-NC allows to erase all unlocked blocks.
It is desirable in case of which you have to implement
Erase operation maximum 32 times.
LH28F004SU-NC enables Two-Byte serial Write
which is operated by three times command input. This
feature can improve system write performance by up to
typically 10 µs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) and a RY »/BY » output pin provide informa-
tion on the progress of the requested operation.
Same as the LH28F008SA, LH28F004SU-NC re-
quires an operation to complete before the next opera-
tion can be requested, also it allows to suspend block
erase to read data from any other block, and allow to
resume erase operation.
The LH28F004SU-NC provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or Ap-
plication Code. Each block has an associated non-vola-
tile lock-bit which determines the lock status of the block.
In addition, the LH28F004SU-NC has a software con-
trolled master Write Protect circuit which prevents any
modifications to memory blocks whose lock-bits are set.
When the device power-up or RP » turns High, Write
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP » turns High, Erase All Un-
locked Blocks can be used. If used, Erase is performed
with reflecting actual lock status, and after that Write
and Block Erase can be used.
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