MC100LVELT23DG 查看數據表（PDF） - ON Semiconductor

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MC100LVELT23DG

3.3 VDual Differential LVPECL/LVDS to LVTTL Translator

ON Semiconductor 

D0 1

D0 2

D1 3

LVPECL LVTTL

D1 4

MC100LVELT23

8 VCC

7 Q0

6 Q1

5 GND

Table 1. PIN DESCRIPTION

Pin

Function

Q0, Q1

D0*, D1*

D0*, D1*

VCC

GND

EP

LVTTL Outputs

Differential LVPECL Inputs

Positive Supply

Ground

Exposed pad must be connected to a

sufficient thermal conduit. Electrically

connect to the most negative supply or

leave floating open.

** Pins will default to VCC/2 when left open.

Figure 1. 8−Lead Pinout (Top View)

and Logic Diagram

Table 2. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

50 kW

Internal Input Pullup Resistor

50 kW

ESD Protection

Human Body Model

Machine Model

CDM

> 1500 V

> 100 V

> 2000 V

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

91

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. Refer to Application Note AND8003/D for additional information.

http://onsemi.com

2

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