PEB2047 查看數據表（PDF） - Siemens AG

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PEB2047

Memory Time Switch Large

Siemens AG 

PEB 2047

PEB 2047-16

1.1 Pin Definitions and Functions

Pin No.

1

3

14

11

10

7

13

12

9

8

15

16

17

4

20

19

18

5

21

28

22

23

39

25

24

Symbol

VSS

SP

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8/FS0

IN9/FS1

IN10/FS2

IN11/FS3

IN12/FS4

IN13/FS5

IN14/FS6

IN15/FS7

A0

A1

CS

VDD

RES

R/W

WR

DS

RD

Input (I)

Output (O)

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Function

Ground (0 V)

Synchronization Pulse: The MTSL is synchronized to

the PCM system via this line.

PCM-Input Ports: Serial data is received at standard

TTL levels.

PCM-Input Ports or Frame (Measuring Inputs): These

inputs can additionally be used as frame evaluation

inputs.

Address Bus Bit 0, 1: These inputs interface to the

systems address bus to select an internal register for a

read or write access. These pins are only active if a

demultiplexed µP interface mode is selected.

Chip Select: A low level selects the MTSL for a register

access operation.

Supply Voltage: 5 V ± 5 %.

Reset: A high signal on this input forces the MTSL into

reset state.

Read/Write: When “high”, identifies a valid µP access as

a read operation. When “low”, identifies a valid µP

access as a write operation (Motorola bus mode).

Write: This signal indicates a write operation (Siemens/

Intel bus mode).

Data Strobe: The rising edge marks the end of a valid

read or write operation (Motorola bus mode).

Read: This signal indicates a read operation (Siemens/

Intel bus mode).

Semiconductor Group

7

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