MC100LVEP14DT 查看數據表（PDF） - ON Semiconductor
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MC100LVEP14DT Datasheet PDF : 9 Pages
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MC100LVEP14
VCC EN VCC CLK1 CLK1 VBB CLK0 CLK0 CLK_SEL VEE
20
19
18
17
16
15
14
13
12
11
1
0
D
Q
1
2
3
4
5
6
7
8
9
10
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20−Lead Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Function
CLK0*, CLK0**
ECL/PECL/HSTL CLK Input
CLK1*, CLK1**
ECL/PECL/HSTL CLK Input
Q0:4, Q0:4
ECL/PECL Outputs
CLK_SEL*
ECL/PECL Active Clock Select Input
EN*
ECL Sync Enable
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
* Pins will default low when left open.
**Pins will default to VCC/2 when left open.
Table 2. FUNCTION TABLE
CLK0
CLK1
CLK_SEL
EN
Q
L
X
L
H
X
L
X
L
H
X
H
H
X
X
X
L
L
L
H
L
L
L
H
H
L*
*On next negative transition of CLK0 or CLK1
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP−20
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
75 kW
37.5 kW
> 2 kV
> 100 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
UL 94 V−0 @ 0.125 in
357 Devices
http://onsemi.com
2
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