M54HC139 查看數據表（PDF） - STMicroelectronics

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M54HC139

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

STMicroelectronics 

M54HC139

M74HC139

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

. HIGH SPEED

tPD = 12 ns (TYP.) AT VCC = 5 V

. LOW POWER DISSIPATION

ICC = 4 µA (MAX.) AT TA = 25 °C

. HIGH NOISE IMMUNITY

VNIH = VNIL = 28 % VCC (MIN.)

. OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

. SYMMETRICAL OUTPUT IMPEDANCE

|IOH| = IOL = 4 mA (MIN.)

. BALANCED PROPAGATION DELAYS

tPLH = tPHL

. WIDE OPERATING VOLTAGE RANGE

VCC (OPR) = 2 V TO 6 V

. PIN AND FUNCTION COMPATIBLE

WITH 54/74LS139

B1R

(Plastic Package)

F1R

(Ceramic Package)

M 1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M 54HC 13 9F 1R

M 74H C1 39 M1 R

M 74HC 13 9B 1R

M 74H C1 39 C1 R

DESCRIPTION

The M54/74HC139 is a high speed CMOS DUAL

TWO LINE TO FOUR LINE DECODER/DEMULTI-

PLEXER fabricated in silicon gate C2MOS technol-

ogy. It has the same high speed performance of

LSTTL combined with true CMOS low power con-

sumption. The active low enable input can be used

for gating or as a data input for demultiplexing ap-

plications. While the enable input is held high, all

four outputs are high independently of the other in-

puts. All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

PIN CONNECTIONS (top view)

INPUT AND OUTPUT EQUIVALENT CIRCUIT

February 1993

NC =

No Internal

Connection

1/9

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