MAX3679A 查看數據表（PDF） - Microsemi Corporation

零件编号

产品描述 (功能)

生产厂家

MAX3679A

+3.3V, Low-Jitter Crystal to LVPECL Clock Generator

Microsemi Corporation 

+3.3V, Low-Jitter Crystal to LVPECL

Clock Generator

Layout Considerations

The inputs and outputs are critical paths for the

MAX3679A, and care should be taken to minimize dis-

continuities on these transmission line. Here are some

suggestions for maximizing the MAX3679A’s perfor-

mance:

• An uninterrupted ground plane should be posi-

tioned beneath the clock I/Os.

• Ground pin vias should be placed close to the IC

and the input/output interfaces to allow a return

current path to the MAX3679A and the receive

devices.

• Supply decoupling capacitors should be placed

close to the MAX3679A supply pins.

• Maintain 100Ω differential (or 50Ω single-ended)

transmission line impedance out of the MAX3679A.

• Use good high-frequency layout techniques and a

multilayer board with an uninterrupted ground

plane to minimize EMI and crosstalk.

Refer to the MAX3679A Evaluation Kit for more information.

Exposed-Pad Package

The exposed pad on the 32-pin TQFN package pro-

vides a very low inductance path for return current trav-

eling to the PCB ground plane. The pad is also

electrical ground on the MAX3679A and must be sol-

dered to the circuit board ground for proper electrical

performance.

Pin Configuration

TOP VIEW

32 31 30 29 28 27 26 25

VCCO_B 1

+

GND 2

24 GND

23 QB1_OE

QB0_OE 3

22 SELA1

SELB1 4

SELB0 5

MAX3679A

21 SELA0

20 QA_OE

QAC_OE 6

MR 7

*EP

19 GND

18 VCC

GNDO_A 8

17 VCCA

9 10 11 12 13 14 15 16

THIN QFN

(5mm × 5mm)

*EXPOSED PAD CONNECTED TO GROUND.

Chip Information

TRANSISTOR COUNT: 10,780

PROCESS: BiCMOS

10 ______________________________________________________________________________________

Share Link: